As a technique of manufacturing a wiring board of multilayer structure, a build-up method has been widely used. The build-up method typically includes the processes of sequentially forming insulating layers and wiring layers repeatedly on both sides of a core substrate. In such a structure, the wiring layers and the insulating layers can be formed to be thin because these layers are stacked by the build-up method. On the other hand, the core substrate requires a thickness large enough for the wiring board to have a certain rigidity. This limits a reduction in thickness of the entire package.
To achieve a further reduction in thickness of the wiring board (semiconductor package), a structure without a core substrate has been employed in recent years. The wiring board having such a structure is called a “coreless substrate”, because the wiring board has no core.
However, a thin substrate such as a coreless substrate involves a problem in that rigidity of the entire substrate is low and thus the substrate easily warps, because there is no core. A considerable extent of warp is observed due to the application of considerable heat to the substrate especially during processes of reflow soldering for connecting terminals of the chip and the substrate and filling an underfill resin during mounting of a semiconductor element (typically, silicon (Si) chip), and reflow soldering during secondary mounting (mounting, on a mother board or the like, the substrate on which the chip is mounted).
Some measures are taken to cope with such an inconvenience. One of the measures is to provide a relatively thick reinforcing member, such as a glass cloth layer, a prepreg layer, or the like, in a substrate, so as to increase the rigidity of the substrate and to suppress a warp of the substrate. In another method, wiring layers in the substrate are designed to have different wiring patterns so that the ratio of a copper (Cu) wiring in each layer is adjusted for a reduction in warp.
As a technique related to the above art, for example, there is known a package for semiconductor device 50 (FIG. 1) which is described in Japanese Laid-open Patent Publication No. 2003-142617 (Patent Document 1). As another technique related to the above art, there is known a semiconductor device 110 (FIG. 35) which is described in Japanese Laid-open Patent Publication No. 2007-149731 (Patent document 2).
As described above, in the state of the art, a thin substrate such as a coreless substrate is advantageous in terms of a reduction in thickness, because the substrate does not need a core base member. On the other hand, a low rigidity of the entire substrate leads to a problem in that the substrate easily warps at the time of mounting a semiconductor element or at the secondary mounting. To cope with this, various measures have been taken heretofore.
However, it is the existing state that the measure of providing a relatively thick reinforcing member, such as a glass cloth layer or the like, in a substrate cannot suffice as a measure for the warp, because the modulus of elasticity and the coefficient of thermal expansion (CTE) of the reinforcing member are different from those of a semiconductor element (of silicon constituting its substrate) to be mounted. Moreover, in the measure of designing wiring layers in the substrate to have different wiring patterns so that the ratio of copper (Cu) in each layer is adjusted, there is a disadvantage in that the adjustment required for each layer is troublesome and thus is not easy.